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HUF75542P3, HUF75542S3S
TM
Data Sheet
June 2000
File Number
4845.2
75A, 80V, 0.014 Ohm, N-Channel, UltraFET Power MOSFETs Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE
JEDEC TO-263AB
Features
* Ultra Low On-Resistance - rDS(ON) = 0.014, VGS = 10V * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models - www.intersil.com * Peak Current vs Pulse Width Curve * UIS Rating Curve
GATE SOURCE DRAIN (FLANGE) HUF75542P3 DRAIN (FLANGE) HUF75542S3S
Symbol
D
Ordering Information
PART NUMBER PACKAGE TO-220AB TO-263AB BRAND 75542P 75542S HUF75542P3 HUF75542S3S
G
S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF75542S3ST.
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified HUF75542P3, HUF75542S3S UNITS V V V A A 80 80 20 75 58 Figure 4 Figures 6, 14, 15 230 1.54 -55 to 175 300 260 W W/oC
oC oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTE: 1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 SABER(c) is a Copyright of Analogy Inc.
HUF75542P3, HUF75542S3S
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 11) VDS = 75V, VGS = 0V VDS = 70V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-220 and TO-263 0.65 62
oC/W oC/W
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
80 -
-
1 250 100
V A A nA
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 10) ID = 75A, VGS = 10V (Figure 9)
2 -
0.012
4 0.014
V
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 2750 700 250 pF pF pF Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 40V, ID = 75A, Ig(REF) = 1.0mA (Figures 13, 16, 17) 150 80 5.7 15 33 180 96 7 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 40V, ID = 75A VGS = 10V, RGS = 3.9 (Figures 18, 19) 12.5 117 50 80 195 195 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 75A ISD = 37.5A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 75A, dISD/dt = 100A/s ISD = 75A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 102 255 UNITS V V ns nC
2
HUF75542P3, HUF75542S3S Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) 80 VGS = 10V ID, DRAIN CURRENT (A) 2 1 THERMAL IMPEDANCE ZJC , NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 0.1 PDM NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 SINGLE PULSE 0.01 10-5 10-4 60
40
20
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
t1 t2 101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000 TC = 25oC IDM , PEAK CURRENT (A) FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 VGS = 10V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FIGURE 4. PEAK CURRENT CAPABILITY
3
HUF75542P3, HUF75542S3S Typical Performance Curves
500 IAS , AVALANCHE CURRENT (A) SINGLE PULSE TJ = MAX RATED TC = 25oC 100 100s
(Continued)
1000 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
ID, DRAIN CURRENT (A)
100
STARTING TJ = 25oC STARTING TJ = 150oC
10
1ms 10ms
1 1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
10 0.001 100 200
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
150 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
150 VGS = 20V VGS = 10V VGS = 7V VGS = 6V
ID , DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
120
120
90
90 VGS = 5V 60
60 TJ = 175oC 30 TJ = 25oC TJ = -55oC 0 2 3 4 5 6 VGS , GATE TO SOURCE VOLTAGE (V)
30
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 1 2 3 4
0 VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE 2.0
1.2 VGS = VDS, ID = 250A 1.0
1.5 VGS = 10V, ID = 75A 1.0
0.8
0.6
0.5 -80
-40
0
40
80
120
160
200
0.4 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
4
HUF75542P3, HUF75542S3S Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A C, CAPACITANCE (pF) 1.1
(Continued)
10000 VGS = 0V, f = 1MHz CISS = CGS + CGD
1.0
1000
COSS CDS + CGD
0.9
CRSS = CGD
0.8 -80
-40
0
40
80
120
160
200
100 0.1
1
10
80
TJ , JUNCTION TEMPERATURE (oC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 40V 8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 50A ID = 25A 0 20 40 60 80 100
2
0 Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
-
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
5
HUF75542P3, HUF75542S3S Test Circuits and Waveforms
(Continued)
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
6
HUF75542P3, HUF75542S3S PSPICE Electrical Model
.SUBCKT HUF75542P3 2 1 3 ;
CA 12 8 4.4e-9 CB 15 14 4.2e-9 CIN 6 8 2.5e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
rev 15 Feb 2000
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 DRAIN 2 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 21 16
RSLC2
5 51 ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 -
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 2.6e-9 LSOURCE 3 7 1.1e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5.5e-3 RGATE 9 20 1.0 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.3e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*230),2.5))} .MODEL DBODYMOD D (IS = 2.5e-12 RS = 2.85e-3 XTI = 5.5 TRS1 = 2e-3 TRS2 = 1e-6 CJO = 3.2e-9 TT = 5.5e-8 M = 0.6) .MODEL DBREAKMOD D (RS = 2.9e-1 TRS1 = 1e-3 TRS2 = 1e-6) .MODEL DPLCAPMOD D (CJO = 3.4e-9 IS = 1e-30 M = 0.8 N = 10) .MODEL MMEDMOD NMOS (VTO = 3.06 KP = 4.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1) .MODEL MSTROMOD NMOS (VTO = 3.5 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.67 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10) .MODEL RBREAKMOD RES (TC1 =1.3e-3 TC2 = -9e-7) .MODEL RDRAINMOD RES (TC1 = 1.1e-2 TC2 = 2.5e-5) .MODEL RSLCMOD RES (TC1 = 4.5e-3 TC2 = 1e-5) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.5e-3 TC2 = -1.1e-5) .MODEL RVTEMPMOD RES (TC1 = -2.75e-3 TC2 = 0) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.0 VOFF= -4.5) VON = -4.5 VOFF= -6.0) VON = -0.5 VOFF= 0.5) VON = 0.5 VOFF= -0.5)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
+
EBREAK 11 7 17 18 87.2 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
DBODY
HUF75542P3, HUF75542S3S SABER Electrical Model
REV 15 Feb 00 template huf75542p3 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (is = 2.5e-12, rs = 2.85e-3, xti = 5.5, trs1 = 2e-3, trs2 = 1e-6, cjo = 3.2e-9, tt = 5.5e-8, m = 0.6) dp..model dbreakmod = (rs = 2.9e-1, trs1 = 1e-3, trs2 = 1e-6) dp..model dplcapmod = (cjo = 3.4e-9, is = 1e-30, m = 0.8, nl = 10) m..model mmedmod = (type=_n, vto = 3.06, kp = 4.8, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.5, kp = 80, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.67, kp = 0.08, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -4.5) DPLCAP 5 sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4.5, voff = -6.0) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5) RSLC1 c.ca n12 n8 = 4.4e-9 c.cb n15 n14 = 4.2e-9 c.cin n6 n8 = 2.5e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 2.6e-9 l.lsource n3 n7 = 1.1e-9
LGATE GATE 1 RLGATE CIN 51 RSLC2 ISCL ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO 8 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 RSOURCE RLSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 DBODY DBREAK 11
LDRAIN DRAIN 2 RLDRAIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -9e-7 res.rdrain n50 n16 = 5.5e-3, tc1 = 1.1e-2, tc2 = 2.5e-5 res.rgate n9 n20 = 1.0 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 4.5e-3, tc2 = 1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.3e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -2.5e-3, tc2 = -1.1e-5 spe.ebreak n11 n7 n17 n18 = 87.2 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/230))** 2.5)) } }
LSOURCE 7
SOURCE 3
8
HUF75542P3, HUF75542S3S SPICE Thermal Model
REV 15 Feb 00 T75542 CTHERM1 th 6 4.1e-3 CTHERM2 6 5 5.5e-3 CTHERM3 5 4 8.6e-3 CTHERM4 4 3 1.5e-2 CTHERM5 3 2 1.6e-2 CTHERM6 2 tl 6.5e-2 RTHERM1 th 6 2.0e-4 RTHERM2 6 5 3.5e-3 RTHERM3 5 4 2.5e-2 RTHERM4 4 3 9.0e-2 RTHERM5 3 2 1.6e-1 RTHERM6 2 tl 2.3e-1
th JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model t75542 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 4.1e-3 ctherm.ctherm2 6 5 = 5.5e-3 ctherm.ctherm3 5 4 = 8.6e-3 ctherm.ctherm4 4 3 = 1.5e-2 ctherm.ctherm5 3 2 = 1.6e-2 ctherm.ctherm6 2 tl = 6.5e-2 rtherm.rtherm1 th 6 = 2.0e-4 rtherm.rtherm2 6 5 = 3.5e-3 rtherm.rtherm3 5 4 = 2.5e-2 rtherm.rtherm4 4 3 = 9.0e-2 rtherm.rtherm5 3 2 = 1.6e-1 rtherm.rtherm6 2 tl = 2.3e-1 }
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
9
HUF75542P3, HUF75542S3S TO-263AB
H1 TERM. 4 D
SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE
E A A1
L2 L1 1 3
L
b e e1
TERM. 4
b1
J1 0.450 (11.43)
c
L3
b2
0.350 (8.89) 0.700 (17.78)
3
1 0.080 TYP (2.03) 0.062 TYP (1.58)
0.150 (3.81)
MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS
INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 A1 0.048 0.052 1.22 1.32 4, 5 b 0.030 0.034 0.77 0.86 4, 5 b1 0.045 0.055 1.15 1.39 4, 5 b2 0.310 7.88 2 c 0.018 0.022 0.46 0.55 4, 5 D 0.405 0.425 10.29 10.79 E 0.395 0.405 10.04 10.28 e 0.100 TYP 2.54 TYP 7 e1 0.200 BSC 5.08 BSC 7 H1 0.045 0.055 1.15 1.39 J1 0.095 0.105 2.42 2.66 L 0.175 0.195 4.45 4.95 L1 0.090 0.110 2.29 2.79 4, 6 L2 0.050 0.070 1.27 1.77 3 L3 0.315 8.01 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-263AB outline dated 2-92. 2. L3 and b2 dimensions established a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.120 inches (3.05mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 10 dated 5-99.
1.5mm DIA. HOLE
4.0mm USER DIRECTION OF FEED 2.0mm 1.75mm C L
TO-263AB
24mm TAPE AND REEL
24mm
16mm
COVER TAPE
40mm MIN. ACCESS HOLE 30.4mm
13mm 330mm 100mm
GENERAL INFORMATION 1. 800 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. 24.4mm
10
HUF75542P3, HUF75542S3S TO-220AB
3 LEAD JEDEC TO-220AB PLASTIC PACKAGE
A OP Q H1 D E1 45o D1 TERM. 4 E A1
INCHES SYMBOL A A1 b b1 c D D1 E E1 e e1 MIN 0.170 0.048 0.030 0.045 0.014 0.590 0.395 MAX 0.180 0.052 0.034 0.055 0.019 0.610 0.160 0.410 0.030 0.100 TYP 0.200 BSC 0.235 0.100 0.530 0.130 0.149 0.102 0.255 0.110 0.550 0.150 0.153 0.112
MILLIMETERS MIN 4.32 1.22 0.77 1.15 0.36 14.99 10.04 MAX 4.57 1.32 0.86 1.39 0.48 15.49 4.06 10.41 0.76 2.54 TYP 5.08 BSC 5.97 2.54 13.47 3.31 3.79 2.60 6.47 2.79 13.97 3.81 3.88 2.84 NOTES 3, 4 2, 3 2, 3, 4 5 5 6 2 -
L1
b1 b c
L 60o 1 2 3
e e1
J1
H1 J1 L L1 OP Q
NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 2 dated 7-97.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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